PROCESSORS & LICENSABLE IP

LICENSABLE IP
PROCESSORS

LICENSABLE IP

All processing cores contain a coherent bus interface providing a unified memory address map with  memory coherency across all processing elements. 

 

Our licensable cores can be implemented with standard cell technologies, while achieving frequencies up to 2.5 GHz.

 

Each processor core contains its own configurable level 1 instruction cache (L1 I-cache), level 1 data cache (L1 D-cache), and L2 cache sizes. In addition, the platform allows a variable number of processing elements to customize the SoC design based on the end user’s application.

 

Multiple privilege levels are supported by each platform core.  This feature enables the implementation of hypervisors and other isolation/security extensions. 

PROCESSORS​

The SB3500® features the Sandblaster® DSP for execution of baseband in software – including physical layer. It has a programmable RF interface, with the capability to capture raw data at 240 M samples/sec. It includes interfaces to LCD, keypad, USIM, SmartCard, Audio codec, IrDA, plus emerging 'critical' features such as add-on memory cards, camera interface, and USB.

SB3500 Feature List

 

  • High Performance, Low-Power Design

    • 1.2 V +/- 10% Core Voltage

    • 65-nm Technology

    • 2.5 / 1.8 V +/- 10% Input/Output Voltage

  • Three SandBlaster® Extended (SBX) DSP Cores

    • Four Hardware Threads per Core

    • 32K-Bytes Instruction Cache per Core

    • 256K-Bytes Data Memory per Core

    • 9.6 Billion MACs per Core @ 600MHz operation

  • Integrated ARM926EJ-S Processor *1

    • 16K-Bytes, each Instruction & Data Cache

    • 32K-Bytes/16K-Bytes Instruction & Data TCM

  • Timers

    • 4 32-Bit Timers per Sandblaster® Core

    • 3 24-Bit, Timers/Pulse Generators Per Sandblaster® Core, cascade-able and configurable for external system clock operation

    • 2 Global 32-Bit general purpose Timers

    • Real-Time Clock (RTC)

    • SoC Watchdog Timer

    • Power Management control timers, for event processing

  • DMA Controllers

    • 12 SBX DMAs, one Per Thread

    • ARM Bus DMA, multi-channel

  • Programmable Interrupt Controller

  • Configurable Dynamic and Static Memory Controllers

    • Supports Synchronous: MDDR, SRAM

    • Supports Asynchronous: SRAM, ROM, NOR/NAND Flash

 

  • Configurable I/O

    • 2 GB External Address Space

    • 32 Dedicated GPIOs, plus 64 multifunction I/Os

  • Two UARTs, one configurable for IRDA (115 Kbps)

  • Serial Peripherals

    • Five SPI™ *2, each with multi-address selects

    • Five I2C™ *3 interfaces

  • Memory Card Interfaces

    • Secure Digital Input/Output

    • Smart Card

  • PS2 Interface (Mouse, Keyboard)

  • Keypad Interface

  • Camera Interface

    • 10-bit interface with internal queue

  • LCD Controller

    • Up to 1024 x 768 Resolution

    • Supports STN, Color STN, HR-TFT, TFT

    • Up to 64K-Colors and 15 Gray Shades

    • Pointer overlay

  • USB OTG Interface

  • AC ´97 / I2S Codec Interface with S/PDIF Support

  • Dedicated RF Data Interfaces

    • Four 16-bit Parallel Ports (Programmable for UL or DL data)

    • DigRF baseband interface

  • External Communications Interface

    • 4K x 16-bit DP memory interface for communications with optional Applications Processor

  • Integrated Device Power Management Unit

*1 ARM926EJ-S is a trademark of ARM Limited.
*2 SPI is a trademark of Motorola, Inc. 
*3 I2C is a trademark of Phillips Semiconductors Corporation

 

Download Feature List here:

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