Optimum Semiconductor processors such as the SB3500® series are powered by Sandblaster® DSP, an indigenously developed digital signal processor by Optimum Semiconductor . It is this key Sandblaster® DSP technology that drives the flexible alternative to traditional dedicated baseband hardware. With this core technology Optimum Semiconductor has addressed one of the biggest challenges in the mobile semiconductor market by providing a highly programmable, high performance, low power chip for mobile devices.
In addition to the Sandblaster® DSP and the Instruction Set Architecture (ISA) innovation, a tightly coupled Sandblaster® IDE provides the industry’s ONLY DSP development flow which is capable of producing production-ready executable software based on high level language ("C") programming.
For these key innovations Optimum Semiconductor has 50+ unique submitted patents, of which 25+ US patents have been granted. Numerous foreign patents have also been issued. In total, when issued worldwide, Optimum Semiconductor will have a patent portfolio of more than 360+ patents.
The GPT Unity Platform is a set of scalable, low power, performance optimized processor cores. The processor cores are implementations of a converged Instruction Set Architecture (ISA), the Unity 1.0 ISA, with a common ISA structure and relevant ISA extensions depending on the class of the processing element selected.
A key attribute of the Unity 1.0 ISA is its ability to efficiently map Heterogeneous System Architecture Intermediate Language (HSAIL) instructions.
All GPT processors include HSA support and the company is now offering world-class HSA-enabled processors to its customers. The HSA enabled IP core which is sampling now in silicon is a first implementation of GPT's 3-in-1 Unity architecture designed for multidimensional signal processing including image and video processing and this licensable IP technology is already passing conformance tests for HSA (Heterogeneous System Architecture).
The Sandblaster® DSP, a Optimum Semiconductor innovation allows development communication systems in software. Rather than designing custom hardware blocks for every function in the communication system, the Sandblaster® DSP is implemented as a compact and power-efficient core, and is replicated to provide a system-on-chip platform (SB3500) tailored for wireless devices. This approach scales well with successive generations of silicon process technology and provides optimum efficiency and programmability.
To address stringent timing constraints, Sandblaster® DSP employs a multithreading technique as an elegant method of servicing events within specified latencies. Uni-processors on the other hand, particularly non-interlocked (i.e. non-transparent) processors, may have significant challenges meeting real-time constraints due to non-interruptible execution sequences. The Sandblaster® approach allows for any thread to be interrupted on an instruction boundary without side effects (i.e. transparent execution). Additionally, any thread can be dynamically programmed to handle an array of interrupt driven events.
The result of this methodology is the ability to develop real-time communication systems, with low power consumption and an efficient development cycle.
From the start, Optimum Semiconductor set off to define a wireless platform that would offer revolutionary capability to handset manufacturers, with the following goals:
Efficiently implement a wide range of advanced communications protocols and multimedia applications
Allow simultaneous execution of computationally intensive tasks in real-time
Provide for a high degree of flexibility and re-use of silicon
Offer a programming environment that is substantially more efficient than traditional DSP programming
To achieve those goals while preserving low power appropriate for handset designs requires employing new techniques at every level of design – architecture and micro architecture, logic and circuit design, plus algorithm and software design. The result is the Sandblaster® Instruction Set Architecture (ISA).
The Sandblaster® Instruction Set Architecture (ISA)
The Sandblaster® ISA employs a number of architectural advancements that deliver a quantum leap in raw DSP performance along with a system design that allows the handset developer to implement real-world communications systems and devices. In the multi-threaded Sandblaster® design, eight (8) hardware threads operate simultaneously – and the software system enables near-limitless software parallelism without the traditional performance penalties associated with task switching. Rather than imposing a cumbersome development or design process on the development team, Optimum Semiconductor provides a standard C language compiler that can directly emit high performance code that does not require assembly language programming or intrinsics. The Sandblaster® architecture also includes a SIMD/Vector DSP unit, a parallel reduction unit, a RISC-based integer unit, and instruction set support for Java execution.
In total, the architectural innovations each contribute to making the Sandblaster® the most powerful, energy efficient C-compliable DSP in the world.
The Sandblaster® DSP, The Sandblaster® IDE provides the industry’s only DSP development flow which is capable of producing production-ready executable software based on high level language (‘C’) programming. Starting with fixed-point C code, the compiler efficiently emits instructions for the Sandblaster instruction set. Through use of semantic analysis techniques in the compiler, the programmer can write C code in a processor-independent manner and focus on the function to be implemented. From there, the compiler can assess if saturated DSP operations are required and generate the correct assembly code for the function. In addition to the compiler, significant instrumentation and analysis tools are available within the IDE to inform the developer of cycle counts, resource utilization, and memory requirements via the built-in architectural simulator.
Run Time Software
Tightly coupled with the Sandblaster® architecture is the Sandblaster® Operating System (SBOST) – a DSP OS kernel designed to work hand-in-hand with the multithreaded Sandblaster™ hardware design. Software threads can be assigned to hardware threads in order to assure that algorithms execute within the timing constraints of the design. When using the 4-core SB3000® SoC, all 32 hardware threads can run at full speed, and each has full access to the quad Multiply/Accumulate per cycle vector unit. Time critical threads can run without interference from memory stalls or external interrupts – significantly improving predictability. This is particularly useful to allow highly complex 4G OFDM based systems or broadband physical layer dataflow and filtering activity to run at full speed regardless of other loading on the processor. Software written with the POSIX pthreads definition can be assigned to hardware threads by the designer, or left to be automatically scheduled at run-time by the thread scheduler.
All together, Optimum Semiconductor's Sandblaster® IDE provides the most productive flow for top-to-bottom communication protocol development.