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Optimum Semiconductor (OST) provides highly-integrated Systems on Chips (SoCs) a broad range of applications. With its powerful embedded artificial intelligence (eAI) algorithms and support for Heterogeneous Systems Architecture (HSA) processing, OST’s products are designed to be ultra-smart and highly efficient.


The company’s SoCs such as the GP8300 are based on the Unity IP Platform from affiliate company General Processor Technologies. The heterogeneous architecture at the heart of Unity forms the basis of a range of next-generation applications.


OST’s SB3500® series of SoCs are powered by the Sandblaster® DSP (digital signal processor), indigenously developed by Optimum Semiconductor. Sandblaster® DSP technology provides a flexible alternative to traditional dedicated baseband hardware.


For these key innovations, Optimum Semiconductor has a broad patent portfolio worldwide.


Unity Platform

The Unity Platform from Optimum Semiconductor affiliate company General Processor Technologies comprises a set of scalable, low-power, performance-optimized processor cores. The processor cores are implementations of a converged Instruction Set Architecture (ISA), the Unity 1.0 ISA, with a common structure and relevant extensions depending on the class of the processing element selected. A key attribute of the Unity 1.0 ISA is its ability to efficiently map Heterogeneous System Architecture Intermediate Language (HSAIL) instructions. Unity IP cores are at the heart of OST's systems-on-chips (SoCs) including the GP8300.

GP8300 SoC

GP8300 SoC

The GP8300 SoC is designed to dramatically reduce chip cost, area, and power consumption for image recognition and object detection in applications such as self-driving cars, surveillance in smart cities and IoT edge devices, and other embedded Artificial Intelligence (eAI) applications.

Created in 28nm technology, the GP8300 includes four 2GHz ‘Great Wall’ CPU cores from General Processor Technologies (GPT) interconnected with a cache coherent memory supporting Heterogeneous Systems Architecture (HSA) processing for a common programming framework. The GP8300 also integrates four of GPT’s 2GHz Variable Length Vector DSP (VLVm1) cores for signal processing applications. Within the chip, the out-of-order CPUs execute control code while very long vectors process data. In addition to these generalized compute units, the chip also integrates two 1GHz ‘Song’ AI accelerators from GPT.

Building on the success of OST’s innovative SB3500 multithreaded heterogeneous computing platform for low-power software defined radio (SDR), the GP8300 represents a new architecture that achieves deep integration of eAI, edge computing, and communications on a single chip. IoT applications can benefit from integrated functionality including worldwide GPS. The chip also includes multiple interfaces such as eSIM. It also supports customization and software upgrades for NB-IoT standards updates. OST provides support for CaffeNet-based training and tools for automatic fixed-point conversion and compression for inference.

SB3500® Series SoC

SB3500 Series SoC

OST’s innovative SB3500 is a multithreaded heterogeneous computing platform for low-power software defined radio (SDR). Powered by three Sandblaster cores, the SB3500® packs sufficient performance to run the most advanced wireless protocols at power-efficiency levels that rival hardware-centric (ASIC) solutions. Combined with its high-level C compiler, intuitive software design tools and the Sandblaster® IDE, the SB3500® is a truly universal, flexible processor, providing the ability design, test and revise in simple, intuitive software development methodology.


OST’s SB3500 processor is an ideal solution for various wireless communication products. It enables OEMs to take wireless devices from design to production in a fraction of the time required by traditional hardware approaches. The SB3500 also addresses the challenge posed by the multiplicity of evolving radio protocols and feature-sets that mark an increasingly complex and volatile marketplace. The SB3500's unmatched combination of flexibility, performance and efficiency make it the platform of choice for emerging convergent devices.

When it comes to creating a multi-protocol device, the SB3500® is the hands-down choice for silicon re-use and efficiency. For unique multimode combinations, standards such as LTE (TDD, FDD), HSPA, HSPA+, UMTS, WCDMA, GSM, GPRS, EDGE, and others, with the opportunity to incorporate Wi-Fi, Bluetooth, DVB-H, or other communications interfaces, the SB3500® creates a new path to implementation that can significantly improve silicon re-use and reduce time to market.



The Sandblaster® DSP, an Optimum Semiconductor innovation, allows development of communication systems in software. Rather than designing custom hardware blocks for every function in the communication system, the Sandblaster® DSP is implemented as a compact and power-efficient core, and is replicated to provide a system-on-chip platform (SB3500) tailored for wireless devices. This approach scales well with successive generations of silicon process technology and provides optimum efficiency and programmability.


To address stringent timing constraints, the Sandblaster® DSP employs a multithreading technique as an elegant method of servicing events within specified latencies. On the other hand, uni-processors, particularly non-interlocked (i.e. non-transparent) processors, may have significant challenges meeting real-time constraints due to uninterruptible execution sequences. The Sandblaster® approach allows for any thread to be interrupted on an instruction boundary without side effects (i.e. transparent execution). Additionally, any thread can be dynamically programmed to handle an array of interrupt-driven events.


The result of this methodology is the ability to develop real-time communication systems, with low power consumption and an efficient development cycle.



From the start, Optimum Semiconductor set off to define a wireless platform that would offer revolutionary capability to handset manufacturers, with the following goals:


  • Efficiently implement a wide range of advanced communications protocols and multimedia applications

  • Allow simultaneous execution of computationally intensive tasks in real-time

  • Provide for a high degree of flexibility and re-use of silicon

  • Offer a programming environment that is substantially more efficient than traditional DSP programming


To achieve those goals while preserving the low power operation needed for handset designs requires employing new techniques at every level of design – architecture and micro architecture, logic and circuit design, and algorithm and software design. The result is the Sandblaster® Instruction Set Architecture (ISA).

The Sandblaster® Instruction Set Architecture (ISA)

The Sandblaster® ISA employs a number of architectural advancements that deliver a quantum leap in raw DSP performance along with a system design that allows the handset developer to implement real-world communications systems and devices. In the multi-threaded Sandblaster® design, eight (8) hardware threads operate simultaneously – and the software system enables near-limitless software parallelism without the traditional performance penalties associated with task switching. Rather than imposing a cumbersome development or design process on the development team, Optimum Semiconductor provides a standard C language compiler that can directly emit high performance code that does not require assembly language programming or intrinsics. The Sandblaster® architecture also includes a SIMD/Vector DSP unit, a parallel reduction unit, a RISC-based integer unit, and instruction set support for Java execution.


In total, the architectural innovations each contribute to making the Sandblaster® the most powerful, energy efficient C-compliable DSP in the world.

Run Time Software

Tightly coupled with the Sandblaster® architecture is the Sandblaster® Operating System (SBOST) – a DSP OS kernel designed to work hand-in-hand with the multithreaded Sandblaster™ hardware design. Software threads can be assigned to hardware threads in order to assure that algorithms execute within the timing constraints of the design. When using the 4-core SB3000® SoC, all 32 hardware threads can run at full speed, and each has full access to the quad Multiply/Accumulate per cycle vector unit. Time critical threads can run without interference from memory stalls or external interrupts – significantly improving predictability. This is particularly useful to allow highly complex 4G OFDM based systems or broadband physical layer dataflow and filtering activity to run at full speed regardless of other loading on the processor. Software written with the POSIX pthreads definition can be assigned to hardware threads by the designer, or left to be automatically scheduled at run-time by the thread scheduler.


In addition, Optimum Semiconductor's Sandblaster® IDE provides the most productive flow for top-to-bottom communication protocol development.

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